1. Technical Field
The present invention relates to a semiconductor device fabrication method and to a semiconductor device.
2. Related Art
Technologies for semiconductor device fabrication methods that improve on-resistances and the like are commonly known. For example, Japanese Patent Application Laid-Open (JP-A) No. H3-236225 recites a technology that improves on-resistance by reducing the thickness of a substrate (a wafer), by the application of background grinding to grind a rear surface (the surface of a side at which device layers are not formed) of the substrate, and increases a contact area between the rear surface of the wafer and a back metal (an electrode formed at the rear surface).
However, when back-grinding is applied as in the technology recited in JP-A No. H3-236225, the transverse strength of the wafer is reduced by microcracks that form in a fracture surface and the like, and there is concern that chip cracks may form and cause breakages.